In the processing of integrated circuits, electrical contact is typically made to isolated active device regions formed within a wafer substrate typically comprising monocrystalline silicon. The active regions are typically connected by high electrically conductive paths or lines which are fabricated above an insulating material formed over the substrate surface. Further, electrical contact is also typically made to other conductive regions received outwardly of the bulk wafer, such as to conductive lines, contact plugs and other devices. To provide electrical connection between two conductive regions, an opening in an insulating layer is typically etched to the desired regions to enable subsequently formed conductive films to connect with such regions. Where the desired region comprises silicon, conductance can be greatly enhanced by forming a conductive metal silicide interface with the silicon region.
The drive for integrated circuits of greater complexity, performance and reduced size has driven designers to shrink the size of devices in the horizontal plane. Yet to avoid excessive current density, the horizontal scaling has not necessarily been accompanied by a reduction in the vertical dimension. This has resulted in an increase of the ratio of device height to device width, something generally referred to as aspect ratio, and particularly with respect to contact openings.
Increased aspect ratio can result in difficulties in the overall etching process typically used to etch openings through insulating materials for making an electrical contact. For example, one common insulating material within or through which electrical contact openings are etched is borophosphosilicate glass (BPSG). Photoresist is typically deposited and patterned over the BPSG to produce openings which will be transferred by subsequent etch to the BPSG. A typical process for etching a contact opening in BPSG includes dry anisotropic etching, with or without plasma. At the conclusion of the etch, the photoresist is stripped from substrate. At the conclusion of the etch and during the strip, native silicon dioxide forms at the base of the contact opening on the silicon. The strip can have a tendency to transform this silicon dioxide into substoichiometric silicon dioxide. In the context of this document, "substoichiometric silicon dioxide" means SiO.sub.x, where "x" is greater than 0 and less than 2.
Oxides of silicon remaining at the base of contact openings can preclude a conductive contact from being formed. Such are typically contended with in one of two ways. For example, it is known that deposition of titanium into the base of a contact opening over silicon dioxide can result in suitable conductive silicide contacts being formed through the oxide upon silicidation anneal if the oxide is suitably thin. Alternately, silicon dioxide can be stripped with a quick wet etch (i.e., using HF or tetramethylammonium hydroxide solutions) or dry etch immediately prior to metal deposition. Unfortunately, such methods do not etch away the substoichiometric silicon dioxide to the degree the stoichiometric silicon dioxide is etched away. Further, silicidation even where the metal is directly deposited onto the oxide is not uniform across the contact where stoichiometric and substoichiometric silicon dioxide are both present. This can lead to varying thickness silicide being formed at the base of the contact, or no silicide in some locations, resulting in increased contact resistance or leakage to the substrate.
While the invention was principally motivated and resulted from achieving solutions to the above-identified problems, the invention is not so limited, with the scope being defined by the accompanying claims as literally worded and interpreted in accordance with the Doctrine of Equivalents.